A novel 36 bit single fault tolerant multiplier using 5 bit moduli
Damu Radhakrishnan, A.P. Preethy · 2002
A large range integer multiplier using a set of small moduli is presented. The multiplier speed is increased by applying logarithmic principles. This is achieved by selecting prime and powers of prime moduli for the residue number system, and by using index calculus techniques on all moduli. The use of powers of prime moduli was instrumental in providing additional moduli needed for single error correction while keeping the size of each individual moduli small.