A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture
Yutaka Arima, Kazuki Mashiko, Keisuke Okada, TAIJI YAMADA, Akira Maeda, Hiromi Notani, Harufusa Kondoh, Shinsuke Kayano · IEEE Journal of Solid-State Circuits · 1991
A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0- mu m double-poly-Si double-metal CMOS technology. The operation speed is higher than 1*10/sup 12/ connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses.>