A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology
K. Imamiya, Y. Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, R. Shirota, S. Aritome, Kazuhiro Shimizu, K. Hatakeyama, Koji Sakui · IEEE Journal of Solid-State Circuits · 1999
A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 /spl mu/m is achieved with 0.25-/spl mu/m STI. The memory cell is shrunk to 0.29 /spl mu/m/sup 2/, which realizes a 130-mm/sup 2/, 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-/spl mu/s first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 /spl mu/s. That realizes 4.4-Mbyte/s programming throughput.