Logic clause analysis for delay optimization
Berhard Rohfleisch, Bernd Wurth, Kurt J. Antreich · 1995
In this paper, we present a novel method for topological delay optimization of combinational circuits.Unlike most previous techniques, optimization is performed after technology mapping.Therefore, exact gate delay information is known during optimization.Our method p erforms incremental network transformations, speci cally substitutions of gate input or output signals by new gates.We present new theory which relates incremental network transformations to combinations of global clauses, and show how to detect such valid clause combinations.Employing techniques which originated in the test area, our method i s c apable to globally optimize large circuits.Comprehensive experimental results show that our method reduces the delay of large standard c ell netlists by 23% on average.In contrast to most other delay optimization techniques, area r e ductions are achieved c oncurrently.