A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory
Kwang Soo Seol, Hee-Soo Kang, Jaeduk Lee, Hyun‐Suk Kim, Byungkyu Cho, Dohyun Lee, Yong-Lack Choi, Nok-Hyun Ju, Changmin Choi, Sung Hoi Hur, Jungdal Choi, Chilhee Chung · 2010
A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.