Studying the impact of application-level optimizations on the power consumption of multi-core architectures
Shah Mohammad Faizur Rahman, Jichi Guo, Akshatha Bhat, Carlos D. García, Majedul Haque Sujon, Qing Yi, Chunhua Liao, Daniel J. Quinlan · 2012
This paper studies the overall system power variations of two multi-core architectures, an 8-core Intel and a 32-core AMD workstation, while using these machines to execute a wide variety of sequential and multi-threaded benchmarks using varying compiler optimization settings and runtime configurations. Our extensive experimental study provides insights for answering two questions: 1) what degrees of impact can application level optimizations have on reducing the overall system power consumption of modern CMP architectures; and 2) what strategies can compilers and application developers adopt to achieve a balanced performance and power efficiency for applications from a variety of science and embedded systems domains.