Removal of redundancy in logic circuits under classification of undetectable faults
Seiji Kajihara, Hiroyuki Shiba, K. Kinoshita · 2003
The authors describe a method for removing redundant elements using test pattern generation. Redundancy in combinational circuits can be identified from the existence of undetectable stuck-at faults. By classifying undetectable faults into three categories according to their properties obtained in the test pattern generation process, some redundant elements can be concurrently removed. The method produces an irredundant circuit efficiently by using these properties. An improved procedure for redundancy removal is outlined to reduce the number of repetitions of test generation performed in the process. Some environmental results for ISCAS 85 benchmark circuits are also shown.>