A full-custom bit-serial multiplier for neural network algorithms
Antonio Francisco Díaz, J.M. Gallardo, V. Rodellar, Victor M. Garca Nieto, M. Hermida, P. Gomez · 2002
Through the present paper, the full custom design of a fixed-point 16-bit, two's complement bit-serial pipelined multiplier is presented. This structure has been designed using a two-phase dynamic logic, based on the massive use of transmission gates and inverters. It has been synthesized using eight macrocells, of three different types, and these, on their turn, are composed of five basic cells. The productivity of the design is high, as the complete structure is composed by 1556 transistor gates, of which only 26 have been physically designed. The resulting lay-out is rather compact, occupying around 1050/spl times/1150 pm in a SP-DM CMOS process of 1.5 /spl mu/m. It implements a non-overlapping bit-recoding algorithm, and may be used both in pipelined and non-pipelined modes. According to timing estimations, it could operate with clock frequencies up to 50 MHz. The application for which it is intended is the design of an Inner Product Processor for the support of Neural Network Algorithms in the Phonetic Encoding of Speech.>