Stuck‐open faults test generation for cmos combinational circuits
Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita · Systems and Computers in Japan · 1991
Abstract This paper proposes a stuck‐open test generation system which generates test patterns with high fault coverage for single stuck‐open faults in CMOS combinational circuits. In the proposed method, although the stuck‐open faults are treated at switch level in each cell consisting of CMOS logic gates, test patterns for the overall circuit are generated at gate level using a path sensitization method. To reduce the number of test patterns, a gate level circuit is partitioned into subcircuits. Also, heuristics are introduced to select a sensitizing path dynamically such that a pair of test vectors could detect many more faults. Finally, some results are presented about test pattern generation for combinational benchmark circuits.