A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O
Michele Borgatti, Francesco Lertora, B. Forêt, L. Calì · 2003
A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. Application-specific bus-mapped coprocessors and flexible I/O peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customisation. The silicon area required by the system is 20 mm/sup 2/ in a 0.18 /spl mu/m CMOS technology. The embedded FPGA accounts for about 40% of the system area.