Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations
Shen‐Fu Hsiao, Ming-Chih Chen, Chia-Shin Tu · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2006
In this paper, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying a new common-subexpression-elimination (CSE) algorithm to the subfunctions that realize the various transformations in AES encryption and decryption. The first category of subfunctions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of subfunctions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the subfunctions by extracting the common factors in the bit-level expressions of these subfunctions. The separate area-reduction effects of combinations, integrations, and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the proposed AES designs can achieve am area reduction rate of about 20% compared with Synopsys optimization results.