Resource efficient 64-bit floating point matrix multiplication algorithm using FPGA
Dayaram Sonawane, Mukul Sutaone, Inayat Malek · 2009
The paper presents a novel methodology to implement resource efficient 64-bit floating point matrix multiplication algorithm using FPGA. Approach uses systolic architecture using four processing element (PE's) that gives tradeoffs between resource utilization and execution time, results in reducing the routing complexity for dense matrix multiplication problems.