A GaAs 12 × 12 bit expandable parallel multiplier LSI using sidewall-assisted closely-spaced electrode technology
Takashi Furutsuka, Kazutoshi Takahashi, M. Ishikawa, Shoko Yano, Asamitsu Higashisaka · 1984
A high speed GaAs 12 × 12 bit expandable parallel multiplier LSI has been designed and fabricated, which can perform within a 4.0 ns critical path delay. The LSI is implemented in depletion mode FET logic gates (BFL and SCFL), because of their high load drivability and large noise margin. Booth's algorithm and Wallace's tree scheme were used for generating partial products and for adding them, respectively. In order to obtain high speed logic operation, the sidewall-assisted closely-spaced electrode technology (SACSET) was developed and successfully applied to the LSI fabrication.