The power7TM processor SoC
Dieter Wendel, Ronald Kalla, Joshua Friedrich, James A. Kahle, Jens Leenstra, Cedric Lichtenau, Balaram Sinharoy, William J. Starke, Victor V. Zyuban · 2010
Introducing POWER7™ the latest member of the IBM POWER™ processor family. A 567 mm2chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256 kB L2 offers the efficiency to support 4× the number of cores within the same power envelope as its predecessor. Supporting over 4 GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32 B per cycle.