The bus interface and paging units of the i860 microprocessor
M.W. Rhodehamel · 2003
The i860 microprocessor is a one-million-transistor, high-performance, 64-b RISC (reduced-instruction-set-computer)-based microprocessor. The performance of the i860 at 40 MHz is 83000 Dhrystones, 24 double-precision MWhetstones, and 10 double-precision MFLOPS on the Linpack benchmark. To support this rate of integer and floating-point execution a bus interface unit and paging unit were designed to provide the needed bus bandwidth. The bus and paging units, in conjunction with the internal data and instruction caches, can provide a 960-Mbyte internal instruction and data bus bandwidth, and a 160-Mbyte external bus bandwidth.>