A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application
Masaharu Ohashi, T. Hashimoto, S. Kuromaru, Michihito Matsuo, T. Mori-iwa, M. Hamada, Yuta Sugisawa, M. Arita, Hironori Tomita, 正幸 星野, Hiroshi Miyajima, Tsuyoshi Nakamura, K.I. Ishida, T. Kimura, Y. Kohashi, TERUHIKO KONDO, Akihiko Inoue, H. Fujimoto, K. Watada, T. Fukunaga · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003
A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.