H.264 decoder on a 16-core processor with shared-memory and massage-passing communications
Yu Zheng, Jiajie Zhang, Ruijin Xiao, Zhiyi Yu, Xiaoyang Zeng · 2012
This paper presents an implementation of H.264 decoder on a 16-core processor. Multi-core architecture emerges as a good solution to tackle with substantially increasing computation complexity in media applications. A dramatic speedup can be achieved utilizing task-level, thread-level and data-level parallelism. As the core number increases, the inter-core communications draws more attention. We integrate both shared-memory and massage-passing inter-core communications in mapping H.264 decoder. Moreover, our approach achieves good energy efficiency. The realized H.264 decoder with throughput of 30fps@720p consumes 506mW when the processor runs at 750MHz with voltage supply of 1.2V.