High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation
Pramod Kumar Meher, Jagdish C. Patra, M.N.S. Swamy · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2007
A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures.