2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor
Toshinari Takayanagi, K. Sawada, Masaru Takahashi, Yusuke Ito, Mona Uchida, Y. Toyoshima, H. Hayashida, Masayuki Norishima · 2002
The authors describe an on-chip cache/TLB macro which can be integrated with highly concurrent RISC (reduced instruction set computer) processors. The macro incorporates TLB, a 16-kbyte instruction cache, and a 16-kbyte two-port data cache. It executes virtual-to-physical address translation and following physical cache access in 12 ns. The total bandwidth is 2.6 Gbyte/s at 80 MHz. A test chip was fabricated with 0.5- mu m double-polysilicon triple-metal CMOS technology.>