High-frequency, at-speed scan testing
Xijiiang Lin, Ron Press, Janusz Rajski, Patrick Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli · IEEE Design & Test of Computers · 2003
The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.