Massively parallel computing system for research and development applications
W. Johnson · 2003
A description of a SIMD (single-instruction multiple-data) processor development system (SPDS) is presented. The SPDS is designed to provide a cost-effective, turn-key solution to users desiring to explore massively parallel computing applications. The SPDS, which is based upon the geometric-arithmetic parallel processor (GAPP) integrated circuit, contains a two-dimensional array of between 2304 and 10368 processing elements. This processing element array operates in a classical single-instruction/multiple-data fashion. The SPDS processing electronics can be connected to any AT-bus-compatible computer via an interface card. The SPDS works in conjunction with an optional frame grabber card to acquire RS-170 imagery and to display processed results on a standard analog monitor. Software bundled with the SPDS runs under the MS-DOS operating system and includes a compiler/linker/microcode generator for the GAPP array, a GAPP utility library in source code form, and a menu-driven user interface with interactive symbolic debugging capability.>