Debugging of behavioral VHDL specifications by source level emulation
Gernot Koch, U. Kebschull, Wolfgang Rosenstiel · 1995
In this paper we present an approach to accelerate the validation speed of behavioral VHDL system specifications through the use of hardware emulation * . The method allows source level debugging of behavioral, algorithmic VHDL in a way similar to source level debugging known from software programming languages. We can set breakpoints in the source code and evaluate the contents of variables by reading the registers of the circuit when a breakpoint is reached.