High-level low power FPGA design methodology
Francis Wolff, Michael J. Knieser, Daniel Weyer, C. Papachristou · 2002
High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology.