Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over ${\rm GF}(2^{m})$ Using Multiple Parity Prediction Schemes
Chiou‐Yng Lee, Pramod Kumar Meher, Jagdish C. Patra · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009
New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.