Design of low latency on-chip communication based on hybrid NoC architecture
Kun-Lin Tsai, Feipei Lai, Chien-Yu Pan, Di-Sheng Xiao, Hsiang-Jen Tan, Hung-Chang Lee · 2010
Bus and mesh based Networks-on-Chip (NoC) are two different architectures of on-chip communication. Each of them has different features and applications. In this paper, we combine these two architectures and construct a hybrid one. In the hybrid architecture, the IP cores with heavy communication affinity are placed in the same subsystem, and a large mesh NoC is partitioned into several subsystems and individual IPs, so that the transmission latency of NoC can be reduced. An efficient partition and mapping algorithm is proposed for the hybrid NoC architecture. Experimental result shows that an average latency improvement of 17.6% can be obtained when compared with the conventional mesh NoC architecture.