Future scaling of processor-memory interfaces
Jung Ho Ahn, Norman Paul Jouppi, Christos Kozyrakis, Jacob Leverich, Robert Schreiber · 2009
Continuous evolution in process technology brings energy-efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets.