Development of a fault model and test algorithms for embedded DRAMs
Manoj Sachdev, Martinus Johannes Wilhelmina Verstraelen · 2002
Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this fault model linear test algorithms of complexity 8N and 9N have been developed.>