Multiplication using the triangular basis representation over GF(2/sup m/)
Robert W. Furness, S.T.J. Fenn, Mohammed Benaissa · 2002
Bit-serial and bit-parallel multiplication in the finite field GF(2/sup m/) are considered. A bit-serial multiplier is proposed which operates in a similar way to the Hasan-Bhargava multiplier (HBM) proposed in 1992 but only one basis transformation is required as compared to two with the HEM. This basis transformation does not add to the latency of the multiplier if a pipelined structure is used. A regular structure to carry out this transformation is presented, derived directly from the irreducible polynomial for the field and which comprises only a number of XOR gates. The theory of the bit-serial multiplier is then extended and a bit-parallel multiplier presented. The proposed bit-parallel multiplier again requires just one basis transformation, the structure of which is identical to the bit-serial case. Both multipliers support VLSI architectures due to their circuit regularities and have lower hardware requirements than HBMs and Massey-Omura multipliers (MOMs). These multipliers are therefore highly suited to use in Reed-Solomon (RS) error-correction codecs.