Stream-interleaved pipelined RISC processor design for SIMD and MIMD system development
T. Killeen, Mehmet Çelenk · 2002
Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a single instruction stream through a simple load/store architecture. Data dependencies are eliminated by introducing NOP instructions in the stream. A longer pipeline increases the proportion of NOPs. These gaps may be used to interleave multiple instruction streams. A typical parallel organization based on message passing via main memory undermines the efficiency of a load/store architecture. The authors propose a method of sharing internal registers between instruction streams, forming a building block for efficient SIMD and MIMD systems.