A Hardware F-Buffer Implementation
Mike Houston, Arcot J. Preetham, Mark Segal · 2005
This paper describes the hardware F-Buffer implementation featured in the latest ATI graphics processors. We discuss the implementation choices made in each chip and the various impleme ntation challenges faced like overflow handling. The F-Buffer was originally intended as a solution for multi-pas s shading. We demonstrate this functionality, comparing it to traditional multi-pass rendering techniques, an d show performance results. Given hardware F-Buffer support, we describe extended uses like order ind ependent blending. We also show how a future F-Buffer implementation might be extended to allow more advanced operatio ns like data filtering.