A flexible parallel architecture for relaxation labeling algorithms
S.-Y. Lin, Z. Chen · IEEE Transactions on Signal Processing · 1992
The design of a flexible parallel architecture for both the discrete relaxation labeling (DRL) algorithm and the probabilistic relaxation labeling (PRL) algorithm is addressed. Through the analysis of parallelism in the computational models of both algorithms, the parallel execution of the algorithms on a flexible parallel architecture is presented. Three basic types of parallel operations are performed in the architecture: simultaneous, pipeline, and systolic. An illustrative example is used to show how the DRL algorithm can be executed on the parallel architecture. In doing so, the processing element (PE) organization and the combiner organization of the architecture are described. The same architecture with programmable functional units is shown to be able to execute the PRL algorithm, too. The performance comparisons between the proposed architecture and some other existing ones are also given.>