An analog VLSI neural network with on-chip perturbation learning
A.J. Montalvo, R.S. Gyurcsik, John J. Paulos · IEEE Journal of Solid-State Circuits · 1997
An analog very large scale integration (VLSI) neural network intended for cost-sensitive, battery-powered, high-volume applications is described. Weights are stored in the analog domain using a combination of dynamic and nonvolatile memory that allows both fast learning and reliable long-term storage. The synapse occupies 4.9 K /spl mu/m/sup 2/ in a 2-/spl mu/m technology. On-chip controlled perturbation-based gradient descent allows fast learning with very little external support. Other distinguishing features include a reconfigurable topology and a temperature-independent feedforward path. An eight-neuron, 64-synapse proof-of-concept chip reliably solves the exclusive-or problem in ten's of milliseconds and 4-b parity in hundred's of milliseconds.