A 5.3 GB/s 32 Mb embedded SDRAM core with slightly boosting scheme
Akira Yamazaki, T. Yamagata, M. Hatakenaka, A. Miyanishi, Isamu Hayashi, Siera A. Tomishima, A. Mangyo, Y. Yukinari, T. Tatsumi, M. Matsumura, Kazutami Arimoto, Masahiro Yamada · 2002
A slightly boosting (SB) scheme has been proposed for improving transistor performance in system LSIs. Using this scheme, a 32 Mb embedded SDRAM core, which operates at a 166 MHz clock frequency, has been developed. The access time of the SDRAM core has also been improved, and 4 cycles of the RAS latency at 166 MHz has been achieved. The multi-select block write (MSBW) scheme is suited to the embedded SDRAM core having a wide data bus, and it improves the performance in graphic applications. The synchronous direct memory access test (SDMAT) circuit makes it easy to evaluate the embedded SDRAM core, and it realizes the 256 b multi-bit test.