A Delay Circuit for Build-Out-Self-Test in 0.18-μm CMOS
Li Tianmao, Hasimoto Toshifumi, Yukinori Kuroki · 2007
This paper describes a digital controlled delay circuit for BOST(build-out-self-test) with picosecond resolution. The proposed circuit operates at 250MHz under 1.8V supply according to Hspice simulation on the extracted layout. The complete design was fabricated in a standard TSMC 0.18μm CMOS process technology. The proposed circuit draws 7mw of static power and occupies an area of 0.09mm2.