A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
Se June Hong, Ostapko · IEEE Transactions on Computers · 1981
A simple procedure to produce a minimum length test set for a parity network is presented. If M is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line.