Design for Testability Using Architectural Descriptions
Vivek Chickermane, J. Lee, Janak H. Patel · 2005
This paper presents techniques to utilize high-level structural, functional and register-transjer information to perform design-for-testability (DFT}. An automatic tool which utilizes VHDL descriptions of the datapath and control unit of sequential circuits to make an intelligent selection of scan pip-pops is described. This DFT tool ADEPT can make design enhancements early in the design phase. Results on four hard-to-test circuits show that very high fault coverages can be achieved by both a gate-level and a high-level test generator on these circuits after scan selection. Fewer scan jlip-flops were chosen as compared to a gate-level partial scan selection.