Extended abstract: an environment for design verification of smart card systems using attack simulation in systemC
Klaus Rothbart, Ulrich Neffe, Christian Steger, R. Weiß, Edgar Rieger, Andreas Muehlberger · 2005
In this paper an environment for design verification of smart cards using security attack simulation in SystemC is presented. The method for automatic instrumentation of the SystemC code is described, also depicted is the process by which design robustness against attacks is verified. This process involves the system behavior analysis using an extended control flow graph. The results discuss the system behavior analysis of a Java Card/spl trade/ Virtual Machine.