Hardware implementation of an artificial neural network
Nazeih M. Botros, Mohammed A. Abdul-Aziz · 2002
A hardware implementation of a fully digital and fully interconnected feedforward backpropagation artificial network using Xilinx field programmable gate arrays (FPGAs) is presented. The network consists of an input layer with five nodes, a single hidden layer with four nodes, and an output layer with two nodes. These nodes are fully interconnected between adjacent layers. Training is done offline on a conventional digital computer where the final values of the weights are obtained. The network is tested successfully by comparing the values of the output nodes for a different input pattern with those obtained from simulating the network on a PC. The number of FPGAs used can be significantly decreased, and the speed can be increased if a 4K or higher family FPGA is used.>