Architectural design of a complex arithmetic signal processor (CASP)
Yogesh Varma, Monte P. Tull · 2004
In this paper, an instruction set architecture is presented for a complex arithmetic signal processor (CASP). CASP is designed to exploit the best features of RISC styled general purpose processors and memory oriented DSP. CASP utilizes the redundant binary (RB) to exploit the single digit carry-propagation property for performance improvement of inner-product unit. Special addressing modes and instructions are designed to provide for faster signal processing. A special register-indirect mode is created for fetching co-processor memory resident dataset elements. The data path on the RB co-processor side is 256-bits wide which allows for processing of large datasets in parallel. Instructions are designed to utilize less than the full width of RB co-processor. The co-processor can perform parallel operations on groups of 8-elements, or two 4-element real TC numbers. The same structure can be alternatively used by instructions for 2-element complex inner-products. An algorithm to detect and correct the bogus or pseudo carry out of RB arithmetic is developed and implemented as a two level hardware process.