Reconfigurable embedded MAC core design for low-power coarse-grain FPGA
Sangjin Hong, Shu-Shin Chin · Electronics Letters · 2003
A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.