An analog on-chip learning circuit architecture of the weight perturbation algorithm
Francesco Diotalevi, Maurizio Valle, G. M. Bo, E. Biglieri, Daniele D. Caviglia · 2000
In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.