A low-area and low-latency network on chip
Xiaofang Wang, Leeladhar Bandi · 2010
With the rapid increase of processing elements (PEs) on a single chip, the communication network poses a major limiting factor for both performance and power consumption in future SoCs. This paper presents a low-area and low-latency wormhole-switching network on chip (NoC). By introducing a new PE-router organization, our design not only reduces the total number of routers for a given number of PEs, but also offers much more routing flexibility compared to existing mesh-based solutions. In our network, each router is shared by four PEs and each general PE has access to four directly-connected routers in addition to the NEWS (North, East, West, South) connections between neighboring PEs. By sharing routers among PEs, the network reduces the average hop count for packets thereby reducing the latency and improving the throughput of the network. Experimental results show that the proposed network reduces the network latency by up to 50.3% for an SoC with 64 PEs. The network saturation point is extended by up to approximately 100%.