Circuit techniques for a wide world I/O path 64 Meg DRAM
Kazuhiro Komatsuzaki, Sho Sukegawa, K.H. Fung, Tetsuro Inui, Teppei Suzuki, R.N. Rountree, J. You, B. Borchers, T. Komatsuzaki, Hisashi Shichijo, H. Tran, David B. Scott · 2002
The high rate data transfer between CPU and memory in future high performance systems requires the 64 Meg DRAM and generations beyond to take a new design approach. Fast RAS access time together with a wider I/O path are key DRAM performances indices for achieving high bandwidth CPU-MEMORY data operations. A novel Hierarchical Multi-Datalines (HMD) Architecture with a wide I/O path and high speed circuit design techniques used to implement this architecture in a 64 Meg DRAM are described.>