Galileo payload 10.23 MHz master clock generation with a Clock Monitoring and Control Unit (CMCU)
Dirk Felbach, D. Heimbuerger, P. Herre, P. Rastetter · 2004
The system concept of the Galileo navigation satellite payload requires a clock monitoring and control unit (CMCU) to provide a master timing reference for the generation of the navigation signal. This frequency is synthesized from one of four atomic clocks, selected by the CMCU to provide a 10 MHz reference. High requirements have to be applied to the frequency synthesizers not to degrade the frequency stability of the atomic clocks and to provide high spectral purity by acting as a clean-up circuit. As the atomic clocks are free running, their frequency offsets have to be corrected by the synthesizer in frequency steps of less than 1e-13 referred to the CMCU output. To solve these requirements, a hybrid synthesizer architecture is presented, consisting of a phase locked loop in conjunction with a DDS to generate an auxiliary frequency that is tuneable with the required fine granularity. Due to the spurious problems with conventional DDS circuits or fractional frequency dividers new noise shaping technologies are applied to shift the spurious energy to higher Fourier frequencies that are filtered out later by the PLL loop bandwidth. Furthermore to optimise the synthesizer performance with respect to Allan deviation and phase noise, the reference source and OCXO behavior have to be taken into account for the design of the loop filter. In this paper, the concept for the frequency synthesizer will be discussed including the higher order noise shaping applied to the generation of the auxiliary frequency and the loop filter design considerations completed by experimental results obtained with the breadboard circuit.