Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)
Manish Goel, Naresh R. Shanbhag · 2002
Presented in this paper are dynamic algorithm transformations (DAT) for systematic design of reconfigurable computing engines. These techniques allow dynamic alteration of algorithm properties in response to input non-stationarities. The input is modeled as a set of states with an underlying probability distribution, /spl Pscr//sub S/. For each input state s, a signal monitoring algorithm (SMA) computes a power-optimal configuration for the signal processing algorithm (SPA) block. A fraction /spl alpha/ of the (SPA) block is hardwired and the remaining (1-/spl alpha/) is reconfigurable. Similarly, the (SMA) block computation is partitioned into a fraction /spl beta/ for the memory and the remaining (1-/spl beta/) for the data path. For the given input state distribution, the optimal values of /spl alpha/ (/spl alpha//sub opt/) and /spl beta/ (/spl beta//sub opt/) are determined. It is shown that for frequency selective filtering (FIR filters), the power savings of 35%-45% can be achieved by a DAT-based reconfigurable system as compared to the traditional design based on the worst-case scenario.