Synthesis of hazard-free asynchronous circuits with bounded wire delays
Luciano Lavagno, Kurt Keutzer, Alberto Luigi Sangiovanni-Vincentelli · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995
This paper introduces a new synthesis methodology for asynchronous sequential control circuits from a high level specification, the signal transition graph (STG). The methodology is guaranteed to generate hazard-free circuits with the bounded wire-delay model, if the STG is live and has the complete state coding property. The methodology exploits knowledge of the environmental delays, speed-independence with respect to externally visible signals, and logic synthesis techniques. A proof that STG persistency is neither necessary nor sufficient for hazard-free implementation is given.>