Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis
Chu Yu, Hwai-Tsu Hu · 2003
We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.