Programmable digital communications receiver architecture for high data rate avionics and ground applications
J. Luecke, M. Jordan · 2002
The architecture for an advanced, modular, all-digital programmable receiver capable of processing bandwidth-efficient digital modulation schemes at data rates well in excess of 100 Mb/s is described. The receiver is designed around a digital, parallel processing architecture to support high throughput rates while being adaptable to both continuous and burst communication systems. Based on the combined use of GaAs and CMOS technologies, a digital architecture that provides significant processing flexibility is presented. The programming of all critical receiver functions and attributes is supported through this architecture. The general concept is based on a set of high-speed programmable and reconfigurable building blocks that provide the user complete control of the demodulation, tracking, and data-processing functions.>