A CMOS-based logic cell for the implementation of self-checking FPGAs
Parag K. Lala, A.P. Singh, A. Walker · 2003
This paper proposes a logic cell that can be used as a building block for online testable FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch (DCVS) logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexer and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults or identical outputs in the presence of fault.