An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm
M. Miyama, Osamu Tooyama, N. Takamatsu, Tsuyoshi Kodake, Kotaro Nakamura, Aya Kato, Junichi Miyakoshi, K. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, Masahiko Yoshimoto · 2003
This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13 /spl mu/m CMOS technology and contains approximately 7 M-transistors on 4.50 mm /spl times/ 3.35 mm area. The estimated power consumption is less than 100 mW at 81 MHz and 1.0 V. It features a gradient descent search (GDS) algorithm that drastically reduces the required computation power to 7 GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.